Stray-Insensitive Sample-Delay-Hold Buffers For High-Frequency Switched-Capacitor Filters

Switched-capacitor (SC) circuits are analog discretetime signal processing circuits. At the front-end of these circuits, the continuous-time input signal has to be transformed into a discrete-time version. In order to optimize the settling speed of the SC circuit by creating step-input settling responses, the input interface circuit has to transform the continuous-time input signal into a uniform-sampled full period sample-and-hold (SH) signal. At the back-end of the SC circuit, the transition from the discrete-time to the continuous-time domain has to be made. Due to the finite circuit time constants of the SC circuit, the output signals will contain continuous-time transients, even for true full period SH input signals. An output interface circuit is required to sample the correct output signal values of the SC circuit at the ends of the settling periods and to transform the obtained signal sample sequence into a full period SH signal. Therefore, the use of these interface circuits is especially of advantage in high-frequency SC circuits. The commonly applied interface circuit is the delayfree sample-and-hold buffer of figure la.